High performance analog-to-digital converters (ADCs) are now widely used in many applications, including RF receivers (e.g., radar) and electronic countermeasures, communication systems, test instrumentation and others, that handle large dynamic ranges of signal amplitudes of a high data rate signals.
Dynamic specifications for ADCs are typically expressed in the frequency domain, using Fast Fourier Transforms (FFTs) to derive the specifications. With reference to FIG. 1, an example fundamental input signal 100 is shown at its carrier frequency 102, and its power amplitude 104 is shown as less than the full scale range 106 of the associated ADC, providing headroom 108, which is important to avoid clipping of the input signal in the case of offsets from the ADC or input signal generator. Spurious-free dynamic range (SFDR) 110 of the ADC is often defined as the distance in dB from the fundamental input signal 100 peak amplitude 104 to the peak spur level 112 in the output frequency spectrum, which could represent noise and is not necessarily limited to harmonic components of the analog input signal 100. An average noise floor 114 may be derived from both the average noise of the ADC and the FFT operation itself. The noise performance of the ADC is expressed as signal-to-noise ratio, or SNR=6.02n+1.76+10 log(m/2), where n=ADC resolution, and in =FFT points, and the signal is the rms (root mean square) power of the fundamental input signal 100, and the noise is the rms sum of all non-fundamental harmonics in the Nyquist band, excluding DC. For a given sampling frequency, fs, the theoretical rms quantization noise in the bandwidth of input frequencies from DC to fs/2 is given as q/√n, where q is the weight of the ADC's least significant bit (LSB) and n is the number of bits.
Two fundamental limitations to maximizing SFDR in a high-speed ADC are the distortion produced by its front end electronics (i.e., amplifier and sample-and-hold circuit) and that produced by nonlinearity in the transfer function of the encoder portion of the ADC. While little can be done externally to the ADC to significantly reduce the inherent distortion caused by its front end, differential nonlinearity (DNL) in the ADC's encoder transfer function can be reduced by the proper use of external techniques. With reference to FIGS. 2A and 2B, DNL error is generally defined as the difference between an actual transfer function step width 200 (e.g., resulting from comparison of the input signal 202 to a precise reference voltage 202a provided by a reference voltage ladder 204 at a comparator circuit 206a as shown in FIG. 2B) and the ideal value of 1 LSB 208 as shown in FIG. 2A, and is often due to mismatches in the ADC's resistance ladder 204 providing threshold reference voltages 204a-204n and its comparator circuits 206a-206n (in a typical 12-bit ADC, a linear voltage step, 1 LSB, is approximately 250 mV).
A well-known technique called dithering is often utilized to maximize SFDR. Dithering is the process of adding an uncorrelated signal, such as pseudo random noise (PRN) or broadband noise, to a desired analog signal prior to the analog input gate of the ADC. Although the injected dither does not eliminate the errors, it randomizes the DNL errors of the ADC, thereby eliminating the concentration of DNL errors at a small number of codes. This technique improves the resolution and linearity of the conversion by effectively smoothing the quantization errors of the ADC's transfer function. However, while spurs are reduced, a commensurate increase in the noise floor occurs. Many conventional systems simply accept degradation of the noise floor, sub-optimizing SFDR to avoid the additional noise. FIG. 3A illustrates a prior art embodiment of a SFDR maximization, wherein a PRN generator 300 generates a random digital signal 302 that is converted to an analog dither signal 304 by a high dynamic range digital-to-analog converter (DAC) 306 coupled to a summer 308, which adds the analog dither signal 304 to an analog input signal 310 before the dithered analog signal 312 is digitized by ADC 314. The random digital signal 302 is subtracted from the converter response at digital subtractor 316.
FIG. 3B shows another common technique for spur reduction, wherein a wideband non-correlated signal 318 is generated using a thermal noise source 320, and then added to the analog input signal 310 by a summer 308. Depending upon on how much noise must be injected, SNR of the ADC 314 may be unduly sacrificed. In this technique, adding noise that is not in the same band as the input signal 310 is important, as otherwise, the benefits of the dithering are at least partially lost. In order to ensure this for most applications, the wideband dither noise 318 may be low-pass filtered 322 so as not to encroach on the frequency band of the input signal 310.
The effect of quantization noise is even more pronounced in broadband data converters. Wider ADC operating bands result in more thermal noise being integrated and impacting dynamic range. Monobit ADCs can provide very wide bandwidth and excellent SFDR but a single monobit has limited dynamic range due to quantization noise. A “sum of monobits” architecture uses M monobits (M being a user selected number), to overcome this limitation. A problem similar to DNL arises if the DC offsets of the respective monobits are not all equal. The sum of monobits architecture splits the incoming analog signal into M paths each of which is summed with unique analog dither, each dither source being independent from the other dither sources, each sum is provided to one of the M monobit ADCs whose outputs are summed to digital number. To ensure high linearity large amounts of dither are used (can exceed 50% of the dynamic range of a given monobit ADC. The large dither reduces spurs to very low levels but adds large amounts of random noise to the sum. Ideally M monobits achieve a 2^(M−1) dynamic range but this is not usually achieved in real-world circuits. The analog noise imparted by the large dithers can reduce the dynamic range by several integer factors.